Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
نویسندگان
چکیده
منابع مشابه
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 μm embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defect...
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The test scheduling problem for built-in self-tested embedded SRAMs (e-SRAMs) when data retention faults (DRFs) are considered is addressed here. We proposed a ‘retention-aware’ test power model by taking advantage of the fact that there is near-zero test power during the pause time for testing DRFs. The proposed test scheduling algorithm then utilises this new test power model to minimise the ...
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Memory testing commonly faces two issues: the characterization of detailed and realistic fault models, and the definition of time-efficient test algorithms able to detect them. Among the different types of algorithms proposed for testing Static Random Access Memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. The continuous evolution of the memory technolog...
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Among the different types of algorithms proposed to test Static Random Access Memories (SRAMs), March Tests have proven to be faster, simpler and regularly structured. A large number of March Tests with different fault coverage have been published. Usually different march tests detect only a specific set of memory faults. The always growing memory production technology introduces new classes of...
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Embedded SRAMs can occupy the majority of the chip area in SoCs. The increased process spreads of modern scaled-down technologies and non-catastrophic defect-related sensitivity to environmental parameters can compromise the stability of SRAM cells, which is quantified by a low Static Noise Margin (SNM). A Stability Fault (SF) can present itself in a cell whose SNM is so small that it can accid...
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ژورنال
عنوان ژورنال: Journal of Electronic Testing
سال: 2005
ISSN: 0923-8174,1573-0727
DOI: 10.1007/s10836-005-6146-1